Credit points: 15

Subject outline

The increasing complexity of digital systems has led to development of modern methodologies in digital design, simulation and production. Collectively known as electronic design automation (EDA), key elements include graphics-based design entry and verification, hardware description languages (HDLs), application specific integrated circuits (ASICs), complex programmable logic devices (CPLDs) and field programmable gate arrays (FPGAs). This subject introduces the electronic design automation process using the current technology in graphical tools for EDA. It will show how digital systems can be described as a hierarchical structure of block diagrams, state machines, flow charts, truth tables and HDL code (VHDL). Designs can then be extensively simulated to check their integrity, and finally compiled and synthesized in a CPLD or FPGA. Hands-on practical work in laboratory classes, assignments and a team project form a major part of the learning in this subject.

FacultyFaculty of Science, Tech & Engineering

Credit points15

Subject Co-ordinatorJim Whittington

Available to Study Abroad StudentsYes

Subject year levelYear Level 5 - Masters

Exchange StudentsYes

Subject particulars

Subject rules

Prerequisites ELE2DDP or Admission into SMELE


Incompatible subjectsN/A

Equivalent subjectsN/A

Special conditionsN/A

Learning resources


Resource TypeTitleResource RequirementAuthor and YearPublisher
ReadingsAdvanced digital logic design: using VHDL, state machines and synthesis for FPGAsRecommendedLee, S 2005THOMSON
ReadingsDesign Recipes for FPGAsRecommendedWilson, P 2007ELSEVIER
ReadingsDigital Systems Design Using VHDLRecommendedRoth, CH, John, LK 20072ND EDN, CL-ENGINEERING
ReadingsFPGAS 101: Everything you need to know to get startedRecommendedSmith, G 2010NEWNES
ReadingsIntroductory VHDL from simulation to synthesisRecommendedYalamanchili, S 2001PRENTICE HALL
ReadingsRapid prototyping of digital systems: SOPC EditionRecommendedHamblen, J, Hall, T & Furman, M 2008SPRINGER
ReadingsVHDL starter's guideRecommendedYalamanchili, S 20052ND EDN, PRENTICE-HALL

Subject options

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Start date between: and    Key dates

Melbourne, 2014, Semester 2, Day


Online enrolmentYes

Maximum enrolment sizeN/A

Enrolment information

Subject Instance Co-ordinatorJim Whittington

Class requirements

Tutorial Week: 31 - 43
One 1.0 hours tutorial per week on weekdays during the day from week 31 to week 43 and delivered via face-to-face.

Lecture Week: 31 - 43
Two 1.0 hours lecture per week on weekdays during the day from week 31 to week 43 and delivered via face-to-face.

Laboratory Class Week: 31 - 43
One 3.0 hours laboratory class per week on weekdays during the day from week 31 to week 43 and delivered via face-to-face.


Assessment elementComments%
one 2-hour examiation40
one design project (1,200 words per student)30
three 600-word assignments30