ele5tav test and verification
TEST AND VERIFICATION
ELE5TAV
Not currently offered
Credit points: 15
Subject outline
Test and verification techniques for modern integrated circuit and digital system design. Topics covered include: reliability and failure rates, reliability as affected by smaller dimensions and faster devices, thermal considerations. Redundancy and fault tolerance, functional and formal verification and fault modelling. Hardware/software co-design, co-verification and co-simulation. Timing and power analysis. Design for testability and ATPG and fault coverage tools, layout issues for testability. Testing methodologies: in-circuit, built in self test, boundary scan, memory testing, embedded system testing. Board-level interconnect testing. Test bench design.
FacultyFaculty of Science, Tech & Engineering
Credit points15
Subject Co-ordinatorJim Whittington
Available to Study Abroad StudentsYes
Subject year levelYear Level 5 - Masters
Exchange StudentsYes
Subject particulars
Subject rules
Prerequisites ELE3DDE and ELE5ICD or ELE5DSD. Enrolment in this unit requires the approval of the Postgraduate Coursework Co-ordinator.
Co-requisitesN/A
Incompatible subjectsN/A
Equivalent subjects ELE51TAV, ELE52TAV
Special conditionsN/A
Learning resources
Readings
| Resource Type | Title | Resource Requirement | Author and Year | Publisher |
|---|---|---|---|---|
| Readings | Digital Circuit Testing and Testability, | Recommended | Lala, P K 1997 | ACADEMIC PRESS |
| Readings | Digital System Test and Testable Design: Using HDL Models and Architectures | Recommended | Navabi, Z 2010 | SPRINGER |
| Readings | Hardware Design Verification: Simulation and Formal Method-Based Approaches, | Recommended | Lam, W K 2005 | PRENTICE HALL |
| Readings | Writing Testbenches: Functional Verification of HDL Models | Recommended | Bergeron, J 2003 | 2ND ED., KLUWER |
Subject options
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