TEST AND VERIFICATION

ELE5TAV

Not currently offered

Credit points: 15

Subject outline

Test and verification techniques for modern integrated circuit and digital system design. Topics covered include: reliability and failure rates, reliability as affected by smaller dimensions and faster devices, thermal considerations. Redundancy and fault tolerance, functional and formal verification and fault modelling. Hardware/software co-design, co-verification and co-simulation. Timing and power analysis. Design for testability and ATPG and fault coverage tools, layout issues for testability. Testing methodologies: in-circuit, built in self test, boundary scan, memory testing, embedded system testing. Board-level interconnect testing. Test bench design.

FacultyFaculty of Science, Tech & Engineering

Credit points15

Subject Co-ordinatorJim Whittington

Available to Study Abroad StudentsYes

Subject year levelYear Level 5 - Masters

Exchange StudentsYes

Subject particulars

Subject rules

Prerequisites ELE3DDE and ELE5ICD or ELE5DSD. Enrolment in this unit requires the approval of the Postgraduate Coursework Co-ordinator.

Co-requisitesN/A

Incompatible subjectsN/A

Equivalent subjects ELE51TAV, ELE52TAV

Special conditionsN/A

Readings

Resource TypeTitleResource RequirementAuthor and YearPublisher
ReadingsDigital Circuit Testing and Testability,RecommendedLala, P K 1997ACADEMIC PRESS
ReadingsDigital System Test and Testable Design: Using HDL Models and ArchitecturesRecommendedNavabi, Z 2010SPRINGER
ReadingsHardware Design Verification: Simulation and Formal Method-Based Approaches,RecommendedLam, W K 2005PRENTICE HALL
ReadingsWriting Testbenches: Functional Verification of HDL ModelsRecommendedBergeron, J 20032ND ED., KLUWER

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