TEST AND VERIFICATION

ELE5TAV

Not currently offered

Credit points: 15

Subject outline

Test and verification techniques for modern integrated circuit and digital system design. Topics covered include: reliability and failure rates, reliability as affected by smaller dimensions and faster devices, thermal considerations. Redundancy and fault tolerance, functional and formal verification and fault modelling. Hardware/software co-design, co-verification and co-simulation. Timing and power analysis. Design for testability and ATPG and fault coverage tools, layout issues for testability. Testing methodologies: in-circuit, built in self test, boundary scan, memory testing, embedded system testing. Board-level interconnect testing. Test bench design.

SchoolEngineering and Mathematical Sciences

Credit points15

Subject Co-ordinatorJim Whittington

Available to Study Abroad/Exchange StudentsYes

Subject year levelYear Level 5 - Masters

Available as ElectiveNo

Learning ActivitiesN/A

Capstone subjectNo

Subject particulars

Subject rules

Prerequisites ELE3DDE and ELE5ICD or ELE5DSD (and Subject Co-ordinator approval)

Co-requisitesN/A

Incompatible subjectsN/A

Equivalent subjectsELE51TAV OR ELE52TAV

Quota Management StrategyN/A

Quota-conditions or rulesN/A

Special conditionsN/A

Minimum credit point requirementN/A

Assumed knowledgeN/A

Readings

Digital System Test and Testable Design: Using HDL Models and Architectures

Resource TypeRecommended

Resource RequirementN/A

AuthorNavabi, Z

Year2010

Edition/VolumeN/A

PublisherSPRINGER

ISBNN/A

Chapter/article titleN/A

Chapter/issueN/A

URLN/A

Other descriptionN/A

Source locationN/A

Writing Testbenches: Functional Verification of HDL Models

Resource TypeRecommended

Resource RequirementN/A

AuthorBergeron, J

Year2003

Edition/Volume2ND ED

PublisherKLUWER

ISBNN/A

Chapter/article titleN/A

Chapter/issueN/A

URLN/A

Other descriptionN/A

Source locationN/A

Digital Circuit Testing and Testability

Resource TypeRecommended

Resource RequirementN/A

AuthorLala, P K

Year1997

Edition/VolumeN/A

PublisherACADEMIC PRESS

ISBNN/A

Chapter/article titleN/A

Chapter/issueN/A

URLN/A

Other descriptionN/A

Source locationN/A

Hardware Design Verification: Simulation and Formal Method-Based Approaches

Resource TypeRecommended

Resource RequirementN/A

AuthorLam, W K

Year2005

Edition/VolumeN/A

PublisherPRENTICE HALL

ISBNN/A

Chapter/article titleN/A

Chapter/issueN/A

URLN/A

Other descriptionN/A

Source locationN/A

Career Ready

Career-focusedNo

Work-based learningNo

Self sourced or Uni sourcedN/A

Entire subject or partial subjectN/A

Total hours/days requiredN/A

Location of WBL activity (region)N/A

WBL addtional requirementsN/A

Graduate capabilities & intended learning outcomes

Graduate Capabilities

DISCIPLINE KNOWLEDGE AND SKILLS
INQUIRY AND ANALYSIS - Creativity and Innovation
INQUIRY AND ANALYSIS - Critical Thinking and Problem Solving
INQUIRY AND ANALYSIS - Research and Evidence-Based Inquiry

Intended Learning Outcomes

01. Identify effective test and verification procedures to minimise the faults introduced in the integrated circuit and digital system manufacturing process.
02. Create advanced simulation test benches to verify the design operation and compliance to the design specification.
03. Analyse and improve test benches to efficiently detect a digital system deficiencies and shorten the system development life cycle.
04. Design automated test benches for regression tests.
05. Design high level transaction based test benches.
06. Design module built-in self-test (BIST).
07. Optimise the automated test pattern generation (ATPG to maximise the fault coverage and minimise the test duration in the integrated circuit and digital system manufacturing process.

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