ele5tav test and verification
TEST AND VERIFICATION
ELE5TAV
Not currently offered
Credit points: 15
Subject outline
Test and verification techniques for modern integrated circuit and digital system design. Topics covered include: reliability and failure rates, reliability as affected by smaller dimensions and faster devices, thermal considerations. Redundancy and fault tolerance, functional and formal verification and fault modelling. Hardware/software co-design, co-verification and co-simulation. Timing and power analysis. Design for testability and ATPG and fault coverage tools, layout issues for testability. Testing methodologies: in-circuit, built in self test, boundary scan, memory testing, embedded system testing. Board-level interconnect testing. Test bench design.
SchoolEngineering and Mathematical Sciences
Credit points15
Subject Co-ordinatorJames Whittington
Available to Study Abroad/Exchange StudentsYes
Subject year levelYear Level 5 - Masters
Available as ElectiveNo
Learning ActivitiesN/A
Capstone subjectNo
Subject particulars
Subject rules
Prerequisites ELE3DDE and ELE5ICD or ELE5DSD (and Subject Co-ordinator approval)
Co-requisitesN/A
Incompatible subjectsN/A
Equivalent subjectsELE51TAV OR ELE52TAV
Quota Management StrategyN/A
Quota-conditions or rulesN/A
Special conditionsN/A
Minimum credit point requirementN/A
Assumed knowledgeN/A
Learning resources
Digital System Test and Testable Design: Using HDL Models and Architectures
Resource TypeBook
Resource RequirementRecommended
AuthorNavabi, Z
Year2010
Edition/VolumeN/A
PublisherSPRINGER
ISBNN/A
Chapter/article titleN/A
Chapter/issueN/A
URLN/A
Other descriptionN/A
Source locationN/A
Writing Testbenches: Functional Verification of HDL Models
Resource TypeBook
Resource RequirementRecommended
AuthorBergeron, J
Year2003
Edition/Volume2ND ED
PublisherKLUWER
ISBNN/A
Chapter/article titleN/A
Chapter/issueN/A
URLN/A
Other descriptionN/A
Source locationN/A
Digital Circuit Testing and Testability
Resource TypeBook
Resource RequirementRecommended
AuthorLala, P K
Year1997
Edition/VolumeN/A
PublisherACADEMIC PRESS
ISBNN/A
Chapter/article titleN/A
Chapter/issueN/A
URLN/A
Other descriptionN/A
Source locationN/A
Hardware Design Verification: Simulation and Formal Method-Based Approaches
Resource TypeBook
Resource RequirementRecommended
AuthorLam, W K
Year2005
Edition/VolumeN/A
PublisherPRENTICE HALL
ISBNN/A
Chapter/article titleN/A
Chapter/issueN/A
URLN/A
Other descriptionN/A
Source locationN/A
Career Ready
Career-focusedNo
Work-based learningNo
Self sourced or Uni sourcedN/A
Entire subject or partial subjectN/A
Total hours/days requiredN/A
Location of WBL activity (region)N/A
WBL addtional requirementsN/A
Graduate capabilities & intended learning outcomes
Graduate Capabilities
Intended Learning Outcomes
Subject options
Select to view your study options…